Design of Fatigue Driving Detection System Based on FPGA

The design of the fatigue driving detection system based on FPGA is a characteristic experimental teaching case of information countermeasure technology major. The design of this system requires students to use Verilog language to realize effective image data extraction, image decoding, grayscale extraction, PERCLOS detection algorithm, SD storage, VGA display, alarm and other functions by calling internal IP core in Quartus II environment. Through the research and development of AC620 platform, FPGA functions such as image acquisition, data storage, algorithm processing, display and alarm are integrated.The purpose of this experiment is to design and implement a large-scale digital system to cultivate students’ sense of innovation and comprehensive quality. through experiments, students can get the interactive engineering training of parallel programming idea and serial programming idea, improve the top-down system top-level design ability, master the latest FPGA technology and artificial intelligence related application cases in the industry, and get the cultivation of innovation and practice ability in interdisciplinary knowledge fusion and cross platform design.