LIU Dong, ZHU Chen, LIN Chaobiao, REN Na, QU Wanyuan. SiC MOSFET Avalanche Reliability Testbench Development[J]. Experiment Science and Technology. DOI: 10.12179/1672-4550.20240162
Citation: LIU Dong, ZHU Chen, LIN Chaobiao, REN Na, QU Wanyuan. SiC MOSFET Avalanche Reliability Testbench Development[J]. Experiment Science and Technology. DOI: 10.12179/1672-4550.20240162

SiC MOSFET Avalanche Reliability Testbench Development

  • With the demand for power SiC MOSFET devices’ teaching experiment about avalanche breakdown robustness and device reliability estimating, a set of test platform have been developed. Firstly, the SiC MOSFET gate drive circuit design and application scheme was proposed. Through establishing the testbench circuit model and parameter simulated, the test circuit board was designed and fabricated. Based on the above, the whole hardware test platform was established and the commercial SiC MOSFET device was experimented. The typical avalanche performance before and after device failure, and various inductance’s influence on device avalanche characterization were studied. The results follow the laws of theory, verifying the possibility of the developed experiment platform. It behaviors strong openness, functional extensibility and low cost, can be used for power device teaching training and innovation research, providing test platform for cultivating outstanding engineer oriented China power device and chip.
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