Abstract: In security application scenarios, data integrity is of paramount concern. As the core memory component of computer systems, the fault tolerance capability of dynamic random access memory (DRAM) memory plays a critical role in data integrity. This paper proposes a fault-tolerant method for multi-bit data errors in memory, based on shortened RS error-correcting codes and integrated with data interleaving, and a corresponding teaching experiment is designed. In basic experiments, students are guided in hardware implementation to promote their mastery of field programmable gate array (FPGA) design techniques. In extended experiments, they are required to deploy the designed and implemented fault-tolerant circuit within the controller circuit, and add a system bus interface module, a fault injection module, and a data interleaving module to promote their mastery of system design and verification techniques. By innovating experimental teaching content and methods, students can better understand and grasp the fault-tolerant design methods of airborne electronic systems, thereby improving their innovative and practical engineering capabilities.