Abstract: To address the difficulty of interpreting non-ideal phenomena in post-layout simulation during integrated-circuit layout design, this work develops a PEX-netlist-driven layout optimization case centered on the high sensitivity of the bridge-capacitor CDAC structure in SAR ADCs to parasitic capacitance. Using a 0.18-μm 8-bit VCM-based SAR ADC as the study object, the ideal weight-transfer relationship of the bridge CDAC and its parasitic-aware counterpart are first established. The effects of MSB parasitics, LSB parasitics, and differential-structure asymmetry on the output are then analyzed. By statistically extracting and estimating the parasitic capacitances of key nodes from the PEX netlist, the non-ideal post-layout output phenomena are correlated with weight deviations, based on which differential parasitic balancing and iterative optimization are carried out in critical layout regions. The results show that, through layout refinement alone, the post-layout ENOB is improved from 5.0 to 7.53, thereby verifying the effectiveness of the weight equations and the proposed methodology. By integrating theoretical derivation, PEX-netlist analysis, layout refinement, and post-layout verification, this case provides a useful reference for understanding parasitic effects, locating error sources, and performing local layout optimization in post-layout analysis of integrated-circuit layouts.