11位多数判决器的层次化设计

Hierarchical Design of 11 bit Majority Judgment

  • 摘要: 利用模块层次化的多数判决算法,设计了11位多数判决器的最简化组合逻辑电路。首先对11个输入变量进行分组,分别对每组变量按一定算法进行设计,然后按层次对变量数进行递进式缩减,最后根据多数判决的要求对所得6个结果变量进行处理以确定输出结果。为验证该设计的有效性,利用Modelsim仿真软件对电路功能进行抽样性检验测试仿真。仿真结果表明,设计的逻辑电路在保证成本最低的情况下实现了11位多数判决的功能。

     

    Abstract: By using the modularized and hierarchical algorithm of majority judgement,the most simplified combination logic diagram of digital circuit of 11bit majority judgment is designed.That is,11 input variables are divided into groups and the logic relationships in each group are structured respectively.Then,the numbers of the variables are reduced hierarchically by step.Finally,the output is decided after handling the 6 outcome variables via majority judgment.To verify the effectiveness of the design,the programme is composed and its function is tested and checked by samples in simulation software Modelsim.The simulation result shows that the designed digital circuit can realize the function of 11bit majority judgment at the lowest cost.

     

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