Abstract: In order to study the communication performance of STT-MRAM channel, Verilog HDL is applied to implement modeling on the channel, which can simulate the read/write error probability of magnetic channel and the high/low impedance of magnetic tunnel junction. A virtual experiment platform based on FPGA is designed, on which polarization code is adopted as channel encoding scheme to encode the information sequence, and then transmit the encoded sequence in the channel. A Fast-SSC decoder is used at receiver, and communication between the upper computer and FPGA is realized through the PCIe interface. The Platform is implemented on Stratix V 5SGXEA7N2F45C2 and 2,200 clocks are consumed for polarization code (256, 220). At the work frequency of 40 MHz, the test speed of the platform can achieve 4.19 Mb/s.